Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology |
Ujwala A. Belorkar1 and S.A.Ladhake2, 1Hanuman Vyayam Prasarak Mandals College of Engineering & Technology,India and 2Sipanas College of Engineering & Technology,India |
Volume : 1 volume number : 2 pdf |
Efficient Hardware Co-Simulation of Down Convertor for Wireless Communication Systems |
Rajesh Mehra and Swapna Devi , NITTTR, India |
Volume : 1 volume number : 2 pdf |
Two Dimensional Modeling of Nonuniformly Doped MESFET Under Illumination |
B.K.Mishra, Lochan Jolly and Kalawati Patil, Thakur College of Engg and Technology,India |
Volume : 1 volume number : 2 pdf |
Minimization of Handoff Latency by Co-ordinate Evaluation Method Using GPS Based Map |
Debabrata Sarddar1, Joydeep Banerjee1, Souvik Kumar Saha1, Tapas Jana2, Utpal Biswas3 and M.K. Naskar1,1Jadavpur University,India,2Netaji Subhash Engg College,India and 3University of Kalyani, India. |
Volume : 1 volume number : 2 pdf |