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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| Power Evaluation of MIPS Architecture using Clock Gating Technique on FPGAs |
| V.Prasanth1, K.Babulu1, and M.Kamaraju2, 1JNTUGV, India, 2Gudlavalleru Engineering College, India |
| Volume : 15 volume number : 3 pdf |
| Detection of Module Integration Errors in Hierarchical Circuit Designs |
| Nicholas Dematteis, Jesus Godinez, Gina Rhoads, and Maddu Karunaratne, University of Pittsburgh, USA |
| Volume : 15 volume number : 3 pdf |
| Power Evaluation of MIPS Architecture using Clock Gating Technique on FPGAs |
| V.Prasanth1, K.Babulu1, and M.Kamaraju2, 1JNTUGV, India, 2Gudlavalleru Engineering College, India |
| Volume : 15 volume number : 3 pdf |