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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effect Transistors in 32 Nanometer Technology |
| Ali Ghorbani and Ghazaleh Ghorbani, Islamic Azad University, Iran |
| Volume : 5 volume number : 5 pdf |
| Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N Decoder by Reversible Technique |
| Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh, Institute of Engineering and Technology, India |
| Volume : 5 volume number : 5 pdf |
| Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Technology |
| Mehdi Masoudi1, Milad Mazaheri1, Aliakbar Rezaei1 and Keivan Navi2, 1Science and Research Branch of IAU, Iran and 2Shahid Beheshti University, Iran |
| Volume : 5 volume number : 5 pdf |
| A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Multiplexer |
| G.Deepika1, P.Rama Krishna2 and K.S.Rao2, 1RRS College of Engineeering & Technology, India and 2ANURAG Group of Institutions, India |
| Volume : 5 volume number : 5 pdf |
| Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applications |
| V. P. Bhale and U. D. Dalal, Sardar Vallabhbhai National Institute of Technology (SVNIT), India |
| Volume : 5 volume number : 5 pdf |