| A New Transistor Sizing Approach for Digital Integrated Circuits Using Firefly Algorithm |
| Nima Talebpour Anaraki, Mehdi Dolatshahi and Mohammad Hossein Nadimi Shahraki, Islamic Azad University, Iran |
| Volume : 6 volume number : 6 pdf |
| A New Transistor Sizing Approach for Digital Integrated Circuits Using Firefly Algorithm |
| Nima Talebpour Anaraki, Mehdi Dolatshahi and Mohammad Hossein Nadimi Shahraki, Islamic Azad University, Iran |
| Volume : 6 volume number : 6 pdf |
| Advanced Verification Methodology for Complex System on Chip Verification [ |
| G.Renuka1, V.Ushashree2 and P.Chandrasekhar Reddy3, 1SREC, India, 2JBIET, India and 3JNTU, India |
| Volume : 6 volume number : 6 pdf |
| Design of a Low-Power 1.65 GBPS Data Channel for HDMI Transmitter |
| Ajay Agrawal and R.S.Gamad, Shri Govindram Seksaria Institute of Technology and Science, India |
| Volume : 6 volume number : 6 pdf |
| Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clock Gating Technique |
| T.Subhashini and M.Kamaraju, Gudlavalleru Engineering College, India |
| Volume : 6 volume number : 6 pdf |
| A New Transistor Sizing Approach for Digital Integrated Circuits Using Firefly Algorithm |
| Nima Talebpour Anaraki, Mehdi Dolatshahi and Mohammad Hossein Nadimi Shahraki, Islamic Azad University, Iran |
| Volume : 6 volume number : 6 pdf |
| Advanced Verification Methodology for Complex System on Chip Verification |
| G.Renuka1, V.Ushashree2 and P.Chandrasekhar Reddy3, 1SREC, India, 2JBIET, India and 3JNTU, India |
| Volume : 6 volume number : 6 pdf |
| Design of a Low-Power 1.65 GBPS Data Channel for HDMI Transmitter |
| Ajay Agrawal and R.S.Gamad, Shri Govindram Seksaria Institute of Technology and Science, India |
| Volume : 6 volume number : 6 pdf |
| Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clock Gating Technique |
| T.Subhashini and M.Kamaraju, Gudlavalleru Engineering College, India |
| Volume : 6 volume number : 6 pdf |