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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| A Systemc/Simulink Co-Simulation Environment of the JPEG Algorithm |
| Walid Hassairi, Moncef Bousselmi, Mohamed Abid and Carlos Valderrama, UMons University of Mons, Belgium |
| Volume : 3 volume number : 2 pdf |
| Finite State Machine based Vending Machine Controller with Auto-Billing Features |
| Ana Monga and Balwinder Singh, Center for Development of Advanced Computing, India |
| Volume : 3 volume number : 2 pdf |
| Bus Encoder for Crosstalk Avoidance in RLC Modeled Interconnects |
| G. Nagendra Babu, Deepika Agarwal, B. K. Kaushik and S. K. Manhas, Indian Institute of Technology - Roorkee, India |
| Volume : 3 volume number : 2 pdf |
| Cell Stability Analysis of Conventional 6T Dynamic 8T SRAM Cell in 45NM Technology |
| K. Dhanumjaya, M. Sudha, MN.Giri Prasad and K.Padmaraju, Jawaharlal Nehru Technological University, India |
| Volume : 3 volume number : 2 pdf |
| Microcontroller Based Testing of Digital IP-Core |
| Amandeep Singh and Balwinder Singh, Center for Development of Advanced Computing, India |
| Volume : 3 volume number : 2 pdf |
| High Speed Continuous-Time Bandpass ??ADC for Mixed Signal VLSI Chips |
| P.A.HarshaVardhini and M.Madhavi Latha, J.N.T.U, India |
| Volume : 3 volume number : 2 pdf |
| A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology |
| Ishit Makwana1 and Vitrag Sheth2, 1Birla Institute of Technology & Science, India and 2Hewlett Packard Global Soft India Pvt. Ltd., India |
| Volume : 3 volume number : 2 pdf |
| Scope of Reversible Engineering at Gate-Level : Fault - Tolerant Combinational Adders |
| M.Bharathi and K.Neelima, Sree Vidyanikethan Engineering College, India |
| Volume : 3 volume number : 2 pdf |
| FPGA Implementation of ADPLL with Ripple Reduction Techniques |
| Manoj kumar and Kusum Lata, Indian Institute of Information Technology - Allahabad, India |
| Volume : 3 volume number : 2 pdf |
| Wishbone Bus Architecture - A Survey and Comparison |
| Mohandeep Sharma and Dilip Kumar, Center for Development of Advanced Computing, India |
| Volume : 3 volume number : 2 pdf |
| An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications |
| P.Rajeswari1, R.Ramesh2and A.R.Ashwatha1, 1Dayanada Sagar College of Engineering, India and 2Saveetha engineering college, India |
| Volume : 3 volume number : 2 pdf |
| Fault Secure Encoder and Decoder with Clock Gating |
| N.Kapileswar and P.Vijaya Santhi, NRI Engineering College, India |
| Volume : 3 volume number : 2 pdf |
| A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation |
| Usha Bhanu.N1 and A.Chilambuchelvan2, 1Anna University, India and 2R.M.D. Engineering college, India |
| Volume : 3 volume number : 2 pdf |
| Design and Noise Optimization of RF Low Noise Amplifier for IEEE Standard 802.11A WLAN |
| Ravinder Kumar1, Munish Kumar2, and Viranjay M. Srivastava1, 1Jaypee University of Information Technology, India and 2Guru Jambheshwar University of Science and Technology, India |
| Volume : 3 volume number : 2 pdf |
| Threshold Voltage Control Schemes in Finfets |
| V. Narendar, Ramanuj Mishra, Sanjeev Rai, Nayana R and R. A. Mishra, MNNIT, India |
| Volume : 3 volume number : 2 pdf |
| Design of Near-Threshold CMOS Logic Gates |
| N. Geetha Rani1, N. Praveen Kumar1, B. Stephen Charles1, P. Chandrasekhar Reddy2 and S.Md.Imran Ali1,1Stanley Stephen College of Engineering & Technology, India and 2JNTUH College of Engineering, India |
| Volume : 3 volume number : 2 pdf |
| Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA |
| Neenu Joseph and P Nirmal Kumar, Anna University, India |
| Volume : 3 volume number : 2 pdf |
| VHDL Design for Image Segmentation using Gabor filter for Disease Detection |
| Rucha R. Thakur, Swati R. Dixit and A.Y.Deshmukh, G.H.Raisoni College of Engineering, India |
| Volume : 3 volume number : 2 pdf |
| Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design |
| Subodh Wairya1, Rajendra Kumar Nagaria2 and Sudarshan Tiwari2, 1Institute of Engineering & Technology, India and 2Motilal Nehru National Institute of Technology, India |
| Volume : 3 volume number : 2 pdf |
| Analog VLSI Implementation of Neural Network Architecture for Signal Processing |
| Neeraj Chasta1, Sarita Chouhan2and Yogesh Kumar2, 1Mewar University, India and 2MLVTEC, India |
| Volume : 3 volume number : 2 pdf |
| A Systemc/Simulink Co-Simulation Environment of the JPEG Algorithm |
| Walid Hassairi, Moncef Bousselmi, Mohamed Abid and Carlos Valderrama, UMons University of Mons, Belgium |
| Volume : 3 volume number : 2 pdf |