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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| A New Efficient FPGA Design of Residue-to-Binary Converter |
| Edem Kwedzo Bankas and Kazeem Alagbe Gbolagade, University for Development Studies, Ghana |
| Volume : 4 volume number : 6 pdf |
| Accelerating System Verilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator |
| Abhishek Jain1,2, Piyush Kumar Gupta1, Hima Gupta2 and Sachish Dhar1, 1STMicroelectronics, India and 2Jaypee Institute of Information Technology, India |
| Volume : 4 volume number : 6 pdf |
| Analysis of Pocket Double Gate Tunnel FET for Low Stand by Power Logic Circuits |
| Kamal K. Jha and Manisha Pattanaik, ABV- Indian Institute of Information Technology and Management, India |
| Volume : 4 volume number : 6 pdf |