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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| An Integrated-Approach for Designing and Testing Specific Processors |
| Cesar Giacomini Penteado1, Edward David Moreno2, Sérgio Takeo Kofuji1, 1University of Sao Paulo (USP), Brazil, and 2Federal University of Sergipe, Brazil |
| Volume : 4 volume number : 5 pdf |
| Low Cost Reversible Signed Comparator |
| Farah Sharmin1, Rajib Kumar Mitra2, Rashida Hasan3, Anisur Rahman4, 1,3University of Dhaka, Bangladesh, 2Patuakhali Science and Technology University, Bangladesh and 4Daffodil International University, Bangladesh |
| Volume : 4 volume number : 5 pdf |
| Low Power Reduced Instruction Set Architecture Using Clock Gating Technique |
| M.Kamaraju and G.Chinavenkateswararao, Gudlavalleru Engineering College, India |
| Volume : 4 volume number : 5 pdf |
| Design and Implementation of Complex Floating Point Processor Using FPGA |
| Murali Krishna Pavuluri and T.S.R. Krishna Prasad and Ch.Rambabu, Gudlavalleru Engineering College, India |
| Volume : 4 volume number : 5 pdf |
| A New Improved MCML Logic for DPA Resistant Circuits |
| A.K.Tripathy, A.Prathiba and V.S.Kanchana Bhaaskaran, Vellore Institute of Technology, India |
| Volume : 4 volume number : 5 pdf |
| Static Power Optimization Using Dual Sub-Threshold Supply Voltages in Digital CMOS VLSI Circuits |
| K.Srilakshmi, Y.Syamala and A.Suvir Vikram, Gudlavalleru Engineering College, India |
| Volume : 4 volume number : 5 pdf |
| Design of Low Power CMOS Logic Circuits Using Gate Diffusion Input (GDI) Technique |
| Y. Syamala, K. Srilakshmi and N. Somasekhar Varma, Gudlavalleru Engineering College, India |
| Volume : 4 volume number : 5 pdf |
| Design of Ultra Low Power 8-Channel Analog Multiplexer Using Dynamic Threshold for Biosignals |
| D.Hari Priya1, P. Rama Krishna2, V. Rajesh1 and K. S. Rao3, 1KL University, India and 1,2,3Anurag Group of Institutions, India |
| Volume : 4 volume number : 5 pdf |
| A 10 dBm-25 dBm, 0.363 mm2 Two Stage 130 nm RF CMOS Power Amplifier |
| Shridhar R. Sahu and A. Y. Deshmukh, G.H.Raisoni College of Engineering, India |
| Volume : 4 volume number : 5 pdf |