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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| A 20 Gb/s Injection-Locked Clock and Data Recovery Circuit |
| Sara Jafarbeiki1, Khosrow Hajsadeghi1 and Naeeme Modir2, 1Sharif University of Technology, Iran and 2University of Tehran, Iran |
| Volume : 5 volume number : 4 pdf |
| CRDOM : Cell Re-Ordering Based Domino On-The-Fly Mapping |
| Sai Praveen Kadiyala and Debasis Samanta, Indian Institute of Technology - Kharagpur, India |
| Volume : 5 volume number : 4 pdf |
| An Operational Amplifier with Recycling Folded Cascode Topology and Adaptive Biasing |
| Saumya Vij1, Anu Gupta1 and Alok Mittal2, 1BITS-Pilani, India and 2STMicroelectronics, India |
| Volume : 5 volume number : 4 pdf |
| Design and Implementation of 4T, 3T and 3T1D DRAM Cell Design on 32 NM Technology |
| Prateek Asthana and Sangeeta Mangesh, JSS Academy of Technical Education, India |
| Volume : 5 volume number : 4 pdf |
| Multisim Design and Simulation of 2.2GHz LNA for Wireless Communication |
| Oluwajobi F. I, Lawal Wasiu, RUFUS GIWA Polytechnic, Nigeria |
| Volume : 5 volume number : 4 pdf |