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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| Stand by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits Using Self Adjustable Voltage Level Circuit |
| Deeprose Subedi and Eugene John, University of Texas at San Antonio, USA |
| Volume : 3 volume number : 5 pdf |
| DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme |
| Majed ValadBeigi, Farshad Safaei and Bahareh Pourshirazi, Shahid Beheshti University G.C, Iran |
| Volume : 3 volume number : 5 pdf |
| Modified March C-With Concurrency in Testing for Embedded Memory Applications |
| Muddapu Parvathi1 , N.Vasantha2 and K.Satya Parasad3, 1M.R.I.T.S, India, 2V.C.E, India and 3J.N.T.U.K, India |
| Volume : 3 volume number : 5 pdf |
| Low Power Dynamic Buffer Circuits |
| Amit Kumar Pandey, Ram Awadh Mishra and Rajendra Kumar Nagaria, M.N.N.I.T, India |
| Volume : 3 volume number : 5 pdf |
| Modeling of Built-In Potential Variations of Cylindrical Surrounding Gate (CSG) MOSFETs |
| Santosh Kumar Gupta and S. Baishya, National Institute of Technology - Assam, India |
| Volume : 3 volume number : 5 pdf |
| Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM |
| Prathima. A1, Kiran Bailey1, K.S.Gurumurthy2, 1BMSCE, India and 2Bangalore University, India |
| Volume : 3 volume number : 5 pdf |
| Design and Implementation of Analog Multiplier with Improved Linearity |
| Nandini A.S, Sowmya Madhavan and Chirag Sharma, Nitte Meenakshi Institute of Technology, India |
| Volume : 3 volume number : 5 pdf |
| High Fin Width Mosfet Using Gaa Structure |
| S.L.Tripathi, Ramanuj Mishra and R.A.Mishra, MNNIT, India |
| Volume : 3 volume number : 5 pdf |
| Design & Analysis of A Charge Re-Cycle Based Novel Lphs Adiabatic Logic Circuits for Low Power Applications |
| Sanjeev Rai1, Govind Krishna Pal2, Ram Awadh Mishra1 and Sudarshan Tiwari3, 1Motilal Nehru National Institute of Technology, Allahabad, India, 2Apache Design Solutions, Noida, India, 3Director National Institute of Technology, India |
| Volume : 3 volume number : 5 pdf |
| A XOR Threshold Logic Implementation Through Resonant Tunneling Diode |
| Nitesh Kumar Dixit and Vinod Kumari, BIET, India |
| Volume : 3 volume number : 5 pdf |
| An Efficient Approach for Four-Layer Channel Routing in VLSI Design |
| Ajoy Kumar Khan1, Bhaskar Das1 and Tapas Kumar Bayen2, 1Assam University, India and 2N. I. S. T, India |
| Volume : 3 volume number : 5 pdf |
| A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology |
| R .H. Talwekar1 and S.S Limaye2, 1DIMAT, India and 2JIT, India |
| Volume : 3 volume number : 5 pdf |
| Device Characterisation of Short Channel Devices and its Impact on CMOS Circuit Design |
| Kiran Agarwal Gupta1, Dinesh K Anvekar2 and Venkateswarlu V3, 1Visvesvaraya Technology University, India, 2 Honeywell Technology Solutions Lab, India and 3UTL Technologies Ltd., India |
| Volume : 3 volume number : 5 pdf |
| Design of a Reconfigurable DSP Processor with Bit Efficient Residue Number System |
| Chaitali Biswas Dutta1, Partha Garai2 and Amitabha Sinha3, 1Girijananda Chowdhury Institute of Management & Technology, India, 2 Indian Statistical Institute, India and 3West Bengal University of Technology, India |
| Volume : 3 volume number : 5 pdf |
| Improved Extended XY On-Chip Routing in Diametrical 2D MEsh NOC |
| Prasun Ghosal and Tuhin Subhra Das, Bengal Engineering and Science University, India |
| Volume : 3 volume number : 5 pdf |