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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits |
| Mouna Karmani1, Chiraz Khedhiri1, Belgacem Hamdi1 and Brahim Bensalem2,1Electronics and Microelectronics Laboratory,Tunisia and 2Intel Corporation, USA |
| Volume : 2 volume number : 3 pdf |
| Test Generation for Analog and Mixed-Signal Circuits Using Hybrid System Models |
| Tarik NAHHAL1 and Thao Dang2,1Hassan II University, Morocco and 2VERIMAG, France |
| Volume : 2 volume number : 3 pdf |
| A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic |
| P.Prasad Rao and K.Lal Kishore, JNTU-Hyderabad, India |
| Volume : 2 volume number : 3 pdf |
| FPGA Implementation of Soft Output Viterbi Algorithm Using Memoryless Hybrid Register Exchange Method |
| R .D. Kadam and S. L. Haridas, RTM Nagpur University, India |
| Volume : 2 volume number : 3 pdf |
| Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power Applications |
| Subhra Dhar1, Manisha Pattanaik1, P. Rajaram2,1ABV-Indian Institute of Information Technology and Management, India and 2Jiwaji University, India |
| Volume : 2 volume number : 3 pdf |
| Power Comparison of CMOS and Adiabatic Full Adder Circuits |
| Y. Sunil Gavaskar Reddy and V.V.G.S.Rajendra Prasad, JNTUniversity, India |
| Volume : 2 volume number : 3 pdf |
| Sub Ten Micron Channel Devices Achieved by Vertical Organic Thin Film Transistor |
| Abdul Rauf Khan1, S.S.K. Iyer2,1Graphic Era University,India and 2IIT-Kanpur, India |
| Volume : 2 volume number : 3 pdf |
| Pipelined Architecture of 2D-DCT, Quantization and ZigZag Process for JPEG Image Compression Using VHDL |
| T.Pradeepthi and Addanki Purna Ramesh, Sri Vasavi Engg College, India |
| Volume : 2 volume number : 3 pdf |
| Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip |
| Rehan Maroofi1,V. N. Nitnaware1 and S. S. Limaye2,1Ramdeobaba Kamla Nehru College of Engg, India and 2Jhulelal Institute of Technology, India |
| Volume : 2 volume number : 3 pdf |
| Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA |
| Veena M.B and M.N.Shanmukha Swamy, SJCE, India |
| Volume : 2 volume number : 3 pdf |
| Design and Implementation of FPGA Based Signal Processing Card |
| Priya Gupta1 and Deepak Gupta2,1Banasthali University, India and 2Alpine System, India |
| Volume : 2 volume number : 3 pdf |
| Design of a CMOS Bandgap Reference with Low Temperature Coefficient and High Power Supply Rejection Performance |
| Abhisek Dey and Tarun Kanti Bhattacharyya, Indian Institute of Technology-Kharagpur, India |
| Volume : 2 volume number : 3 pdf |
| Area Optimized FPGA Implementation for Generation of Radar Pulse Compression Sequences |
| P. Tirumala rao1, P. Siva kumar1, Y.V. Apparao2, Y. Madhu babu2,1Vignan institute of information technology, India and 2GITAM University, India |
| Volume : 2 volume number : 3 pdf |
| Software and Hardware Design Challenges in Automotive Embedded System |
| Rajeshwari Hegde1, Geetishree Mishra1, K S Gurumurthy2,1BMS College of Engineering, India and 2UVCE, India |
| Volume : 2 volume number : 3 pdf |
| Power Aware Physical Model for 3D ICs |
| Yasmeen Hasan, Integral University, India |
| Volume : 2 volume number : 3 pdf |
| Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate Stack |
| Rakhi Narang1, Manoj Saxena1, R.S.Gupta2and Mridula Gupta1,1University of Delhi, India and 2Maharaja Agrasen Institute of Technology, India |
| Volume : 2 volume number : 3 pdf |
| Brauns Multiplier Implementation using FPGA with Bypassing Techniques |
| Anitha R and Bagyaveereswaran V, VIT University, India |
| Volume : 2 volume number : 3 pdf |
| Modelling and Simulation of 128-Bit Crossbar Switch for Network On Chip |
| Mohammad Ayoub Khan1 and Abdul Quaiyum Ansari2, 1Ministry of Communications and Information Techology, India and 2Jamia Millia Islamia, India |
| Volume : 2 volume number : 3 pdf |
| Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire MOSFET |
| Rajni Gautam1, Manoj Saxena1, R.S.Gupta2and Mridula Gupta1, 1University of Delhi, India and 2Maharaja Agrasen Institute of Technology, India |
| Volume : 2 volume number : 3 pdf |
| Reducing power in using different technologies using FSM architecture |
| Himani Mitta, Dinesh Chandra and Sampath Kumar, J.S.S.Academy of Technical Education, India |
| Volume : 2 volume number : 3 pdf |