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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| A New Full Adder Cell for Molecular Electronics |
| Mehdi Ghasemi, Mohammad Hossein Moaiyeri and Keivan Navi, Shahid Beheshti University G.C., Iran |
| Volume : 2 volume number : 4 pdf |
| A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates |
| Md. Sazzad Hossain1, Md. Rashedul Hasan Rakib1, Md. Motiur Rahman1,A. S. M. Delowar Hossain1 and Md. Minul Hasan2, 1Mawlana Bhashani Science & Technology University, Bangladesh and 2Amader Ltd, Bangladesh |
| Volume : 2 volume number : 4 pdf |
| FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC |
| Bolla Leela Naresh, N.V.Narayana Rao and Addanki Purna Ramesh, Sri Vasavi Engg College, India |
| Volume : 2 volume number : 4 pdf |
| Design of Reversible Sequential Circuit Using Reversible Logic Synthesis |
| Md. Belayet Ali, Md. Mosharof Hossin and Md. Eneyat Ullah, Mawlana Bhashani Science and Technology University, Bangladesh |
| Volume : 2 volume number : 4 pdf |
| Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate |
| Manoj Kumar1, Sandeep K. Arya1 and Sujata Pandey2,1Guru Jambheshwar University of Science & Technology, India and 2Amity University, India |
| Volume : 2 volume number : 4 pdf |
| Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level |
| M.S.Suma1 and K.S.Gurumurthy2, 1R.V.College of Engineering, India and 2U.V.College of Engineering, India |
| Volume : 2 volume number : 4 pdf |
| A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Physical Design Implementation |
| Vasantha Kumar B.V.P1 , N. S. Murthy Sharma2 , K. Lal Kishore3 and Jibanjeet Mishra1, 1 Synopsys (India) Pvt. Ltd, India, 2 SV Institute of Engineering and Technology, India and 3 JNT University, India |
| Volume : 2 volume number : 4 pdf |
| VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology |
| Rita M. Shende and Pritesh R. Gumble, Sipna's College of Engineering & Technology, India |
| Volume : 2 volume number : 4 pdf |
| An Efficient FPGA Implemenation of MRI Image Filtering and Tumour Characterization Using XILINX System Generator |
| S. Allin Christe, M.Vignesh and A.Kandaswamy, PSG College of Technology, India |
| Volume : 2 volume number : 4 pdf |
| Design and ASIC Implemenatation of DUC/DDC for Communication Systems |
| Naagesh S. Bhat, Green Mil International Ltd., India |
| Volume : 2 volume number : 4 pdf |
| Low Power Low Voltage Bulk Driven Balanced OTA |
| Neha Gupta, Sapna Singh, Meenakshi Suthar and Priyanka Soni, Mody Institute of Technology and Science, India |
| Volume : 2 volume number : 4 pdf |
| Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell |
| Viplav A. Soliv and Ajay A. Gurjar, Sipna's college of Engineering & Technology, India |
| Volume : 2 volume number : 4 pdf |
| A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs |
| Ramya Menon C. and Vinod Pangracious, Rajagiri School of Engineering & Technology, India |
| Volume : 2 volume number : 4 pdf |
| Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology |
| Rajendra Prasad S1, B K Madhavi2 and K Lal Kishore3, 1ACE Engineering College, India, 2GCET, India and 3JNT University, India |
| Volume : 2 volume number : 4 pdf |
| Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization |
| Bhavana Pote1,V. N. Nitnaware1,and S. S. Limaye2, 1Ramdeobaba Kamla Nehru College of Engg, India and 2Jhulelal Institute of Technology, India |
| Volume : 2 volume number : 4 pdf |