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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture |
| Hanie Ghaedrahmati and Khosrow Hajsadeghi, Sharif University of Technology, Iran |
| Volume : 3 volume number : 6 pdf |
| Generic System Verilog Universal Verification Methodology Based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPS/SOCS |
| Abhishek Jain1,2 Giuseppe Bonanno1, Hima Gupta2 and Ajay Goyal3, 1STMicroelectronics, India, 2Jaypee Institute of Information Technology (JIIT), India and 3Cadence Design System, India |
| Volume : 3 volume number : 6 pdf |
| Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates |
| H R Bhagyalakshmi and M K Venkatesha, Visvesvaraya Technological University, India |
| Volume : 3 volume number : 6 pdf |
| Performance Evaluation of Throughput Maximization in MC-CDMA for 4G Standard |
| Hema Kale1 C.G. Dethe2 and M.M. Mushrif3, 1Jhulelal Institute of Technology, India, 2Priyadarshni Institute of Engineering and Technology, India, 3Yashwantrao Chavan College of Engineering, India |
| Volume : 3 volume number : 6 pdf |
| Design and VLSI Implementation of Anticollision Enabled Robot Processor Using RFID Technology |
| Joyashree Bag, Rajanna K M and Subir Kumar Sarkar, Jadavpur University, India |
| Volume : 3 volume number : 6 pdf |
| Design of Reversible Multipliers for Linear Filtering Applications in DSP |
| Rakshith Saligram1 and Rakshith T.R2, 1B.M.S College of Engineering, India and 2R. V College of Engineering, India |
| Volume : 3 volume number : 6 pdf |
| Synthesis Optimization for Finite State Machine Design in FPGAs |
| R.Uma and P.Dhavachelvan, Pondicherry University, India |
| Volume : 3 volume number : 6 pdf |