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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| High Speed Multiple Valued Logic Full Adder Using Carbon Nano Field Effect Transistor |
| Ashkan Khatir, Shaghayegh Abdolahzadegan and Iman Mahmoudi, Islamic Azad University, Iran |
| Volume : 2 volume number : 1 pdf |
| Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function |
| Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav, Kamalesh Yadav and Devendra Giri, National Institute of Technology - Hamirpur, India |
| Volume : 2 volume number : 1 pdf |
| Physical Scaling Limits of FinFET Structure: A Simulation Study |
| Gaurav Saini and Ashwani K Rana, National Institute of Technology - Hamirpur, India |
| Volume : 2 volume number : 1 pdf |
| Design and Implementation of Area and Power Optimised Novel Scanflop |
| R.Jayagowri1 and K.S.Gurumurthy2, 1Jawaharlal Nehru Technological University, India and 2Visveswaraya College of Engineering, India |
| Volume : 2 volume number : 1 pdf |
| Optimization Techniques for Source Follower Based Track-and-Hold Circuit for High Speed Wireless Communication |
| Manoj Kumar1 and Gagnesh Kumar2, 1Vidya College of Engineering, India and 2NIT - Hamirpur, India |
| Volume : 2 volume number : 1 pdf |
| Impact of Strain and Channel Thickness on Performance of Biaxial Strained Silicon MOSFETs |
| Neha Sharan and Ashwani K.Rana, National Institute of Technology - Hamirpur, India |
| Volume : 2 volume number : 1 pdf |
| Design of a high frequency low voltage CMOS operational amplifier |
| Priyanka Kakoty, Tezpur University, India |
| Volume : 2 volume number : 1 pdf |
| Design Approach for Fault Tolerance in FPGA Architecture |
| Shweta S. Meshram1 and Ujwala A. Belorkar2, 1Government College of Engineering & Technology, Amravati, India and 2Hanuman Vyayam Prasarak Mandal's College of Engineering & Technology, India |
| Volume : 2 volume number : 1 pdf |
| Design and Analysis of Second and Third Order PLL at 450MHz |
| B. K. Mishra, Sandhya Save and Swapna Patil, Mumbai University, India |
| Volume : 2 volume number : 1 pdf |
| Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology |
| Ms. Ujwala A. Belorkar1 and S.A.Ladhake2, 1Hanuman Vyayam Prasarak Mandal's College of Engineering & Technology, India and 2Sipana's College of Engineering & Technology, India |
| Volume : 2 volume number : 1 pdf |