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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| Deadlock Recovery Technique in Bus Enhanced NOC Architecture |
| Saeid Sharifian Nia1, Abbas Vafaei1 and Hamid Shahimohamadi2, 1University of Isfahan, Iran and 2Shahid Beheshti University, Iran |
| Volume : 3 volume number : 4 pdf |
| Design and Implementation A different Architectures of mixcolumn in FPGA |
| Sliman Arrag, Abdellatif Hamdoun, Abderrahim Tragha and Salah eddine Khamlich, Universite Hassan II Mohammedia, Morocco |
| Volume : 3 volume number : 4 pdf |
| Delay Error with Meta - Stability Detection and Correction Using CMOS Transmission Logic |
| Bhawna Kankane, Sandeep Sharma and Navaid Zafar Rizvi, Gautam Buddha University, India |
| Volume : 3 volume number : 4 pdf |
| FPGA Implementation of Efficient VLSI Architecture for Fixed Point 1-D DWT Using Lifting Scheme |
| Durga Sowjanya1, K N H Srinivas1 and P Venkata Ganapathi2, 1Sri Vasavi Engineering College, India and 2Quartics Technologies Pvt Ltd, India |
| Volume : 3 volume number : 4 pdf |
| Improved Algorithm for Throughput Maximization in MC-CDMA |
| Hema Kale1, C.G. Dethe2 and M.M. Mushrif3,1Jhulelal Institute of Technology, India, 2Priyadarshni Institute of Engineering and Technology, India and 3Yashwantrao Chavan College of Engineering, India |
| Volume : 3 volume number : 4 pdf |
| Shield Insertion to Minimize Noise Amplitude in Global Interconnects |
| Kalpana.A.B1 and P.V.Hunagund2, 1Bangalore Institute of Technology, India and 2Gulbarga University, India |
| Volume : 3 volume number : 4 pdf |
| Design of Low Power Sigma Delta ADC |
| Mohammed Arifuddin Sohel1, K. Chenna Kesava Reddy2, Syed Abdul Sattar3, 1Muffakham Jah College of Engineering and Technology, India, 2TKR College of Engineering, India and 3Royal Institute of Technology and Sciences, India |
| Volume : 3 volume number : 4 pdf |
| Novel Sleep Transistor Techniques for Low Leakage Power Peripheral Circuits |
| Rajani H.P.1 and Srimannarayan Kulkarni2, 1KLESs College of Engineering and Technology, India and 2M.S. Ramaiah Institute of Technology, India |
| Volume : 3 volume number : 4 pdf |
| Universal Rotate Invert Bus Encoding for Low Power VLSI |
| Shankaranarayana Bhat M and D. Yogitha Jahnavi, Manipal University, India |
| Volume : 3 volume number : 4 pdf |
| Effect of Equal and Mismatched Signal Transition Time on Power Dissipation in Global VLSI Interconnects |
| Devendra Kumar Sharma1, Brajesh Kumar Kaushik2, and R.K.Sharma3, 1Meerut Institute of Engineering and Technology, India, 2Indian Institute of Technology - Roorkee, India and 3National Institute of Technology, India |
| Volume : 3 volume number : 4 pdf |
| Magnetic Resonance Brain Image Segmentation |
| M.C.Jobin Christ1 and R.M.S.Parvathi2, 1Adhiyamaan College of Engineering, India and 2Sengunthar College of Engineering, India |
| Volume : 3 volume number : 4 pdf |
| Logic Optimization Using Technology Independent MUX Based Adders in FPGA |
| R.Uma and P.Dhavachelvan, Pondicherry University, India |
| Volume : 3 volume number : 4 pdf |