 |
AIRCC Digital Library |
 |
Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
volume - 1 - 1
volume - 1 - 2
volume - 1 - 3
volume - 1 - 4
volume - 2 - 1
volume - 2 - 2
volume - 2 - 3
volume - 2 - 4
volume - 3 - 1
volume - 3 - 2
volume - 3 - 3
volume - 3 - 4
volume - 3 - 5
volume - 3 - 6
volume - 4 - 1
volume - 4 - 2
volume - 4 - 3
volume - 4 - 4
volume - 4 - 5
volume - 4 - 6
volume - 5 - 1
volume - 5 - 2
volume - 5 - 3
volume - 5 - 4
volume - 5 - 5
volume - 5 - 6
volume - 6 - 1
volume - 6 - 2
volume - 6 - 3
volume - 6 - 4
volume - 6 - 5
volume - 6 - 6
volume - 7 - 1
volume - 7 - 3
volume - 7 - 4
volume - 7 - 5
volume - 8 - 1
volume - 8 - 2
volume - 8 - 3
volume - 9 - 1
volume - 9 - 2
volume - 9 - 3
volume - 9 - 4
volume - 9 - 5
volume - 10 - 1
volume - 10 - 2
volume - 10 - 3
volume - 10 - 4
volume - 10 - 5
volume - 11 - 5
volume - 11 - 6
volume - 13 - 6
volume - 14 - 2
volume - 15 - 3
| Design of Three Bit Analog-To-Digital Converter (ADC) Using Spatial Wavefunction Switched (SWS) FETS |
| Supriya Karmakar, Intel Corporation, USA |
| Volume : 4 volume number : 3 pdf |
| Hardware Efficient Scaling Free Vectoring and Rotational Cordic for DSP Applications |
| Anita Jain and Kavita Khare, MANIT, India |
| Volume : 4 volume number : 3 pdf |
| Low Power Dual Edge - Triggered Static D Flip-Flop |
| Anurag, Gurmohan Singh and V. Sulochana, Centre for Development of Advanced Computing, India |
| Volume : 4 volume number : 3 pdf |
| Crosstalk Minimization for Coupled RLC Interconnects Using Bidirectional Buffer and Shield Insertion |
| Damanpreet Kaur and V.Sulochana, Centre for Development of Advanced Computing, India |
| Volume : 4 volume number : 3 pdf |
| CMOS Low Power Cell Library for Digital Design |
| Kanika Kaur1 and Arti Noor2, 1JJTU, India and 2CDAC, India |
| Volume : 4 volume number : 3 pdf |
| Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit |
| Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A Kulkarni, H.R.Bhagyalakshmi and M.K. Venkatesha, Visvesvaraya Technological University, India |
| Volume : 4 volume number : 3 pdf |
| Design and Implementation of Car Parking System on FPGA |
| Ramneet Kaur and Balwinder Singh, Centre for Development of Advanced Computing, India |
| Volume : 4 volume number : 3 pdf |
| A Rail-To-Rail Hign Speed Class-AB CMOS Buffer with Low Power and Enhanced Slew Rate |
| Sadhana Sharma, Abhay Vidyarthi and Shyam Akashe, ITM University, India |
| Volume : 4 volume number : 3 pdf |
| Design of a Programmable Low Power Low Drop-Out Regulator |
| Jayanthi Vanama1 and G.L.Sampoorna2, 1Powerwave Technologies Pvt. Ltd., India and 2CONEXANT Systems Pvt. Ltd., India |
| Volume : 4 volume number : 3 pdf |
| Design and Performance Analysis of ZBT SRAM Controller |
| Smriti Sharma and Balwinder Singh, Centre for Development of Advanced Computing, India |
| Volume : 4 volume number : 3 pdf |
| Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter |
| Arun Kumar Sunaniya and Kavita Khare, MANIT, India |
| Volume : 4 volume number : 3 pdf |
| Power Efficient Carry Propagate Adder |
| Laxmi Kumre, Ajay Somkuwar and Ganga Agnihotri, MANIT, India |
| Volume : 4 volume number : 3 pdf |
| Enhancing Multiplier Speed in Fast Fourier Transform Based on Vedic Mathematics |
| R.P.Meenaakshi Sundari, D.Subathra and M.S.Dhanalaxmi, Sasurie College of Engineering, India |
| Volume : 4 volume number : 3 pdf |